
I2C RTC with Trickle Charger
14
Maxim Integrated
DS1340
Chip Information
PROCESS: CMOS
SUBSTRATE CONNECTED TO GROUND
Thermal Information
Theta-JA: 170°C/W (0.150in SO)
Theta-JC: 40°C/W (0.150in SO)
Theta-JA: 221°C/W (SOP)
Theta-JC: 39°C/W (SOP)
Theta-JA: 89.6°C/W (0.300in SO)
Theta-JC: 24.8°C/W (0.300in SO)
Handling, PC Board Layout,
and Assembly
The DS1340C package contains a quartz tuning-fork
crystal. Pick-and-place equipment may be used, but
precautions should be taken to ensure that excessive
shocks are avoided. Exposure to reflow is limited to 2
times maximum. Ultrasonic cleaning should be avoided
to prevent damage to the crystal.
Avoid running signal traces under the package, unless
a ground plane is placed between the package and the
signal line. All N.C. (no connect) pins must be connect-
ed to ground.
Moisture-sensitive packages are shipped from the facto-
ry dry-packed.Handling instructions listed on the pack-
age label must be followed to prevent damage during
reflow. Refer to the IPC/JEDEC J-STD-020 standard for
moisture-sensitive device (MSD) classifications.
1
2
3
4
8
7
6
5
VCC
FT/OUT
SCL
SDA
VBACKUP
GND
X2
X1
TOP VIEW
SO,
μSOP
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
SCL
SDA
GND
VBACKUP
N.C.
SO (300 mils)
FT/OUT
VCC
N.C.
DS1340
DS1340C
Pin Configurations
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN NO.
8 SO (150 mils)
S8+2
8 SOP
U8+1
16 SO (300 mils)
W16#H2
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character,
but the drawing pertains to the package regardless of RoHS status.